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1 publication date: february 2005 sdd00032aem data sheet semiconductor company matsushita electric industrial co., ltd. MN6627933 part no. package code no. lqfp100 - p - 1414
MN6627933 2 sdd00032aem contents ? overview ?????????????????????????????????????????. 3 ? features ?????????????????????????????????????..???? 3 ? applications ???????????????????????????????????????? 4 ? application circuit ?????????????????????????????????????.. 5 ? block diagram ??????????????????????????????????????? 6 ? pin assignment ??????????????????????????????????????. 7 ? pin descriptions ??????????????????????????????????????. 8 ? absolute maximum ratings ?????????????????????????????????. 12 ? operating supply voltage r ange ?????????????????? ????????????? 12 ? electrical characteristics ??????????????????????????????????.. 14
MN6627933 3 sdd00032aem mn662793 silicon cmos ic ? overview the MN6627933 is a signal processing lsi for cds. it incorporates an optical servo (focus, tracking, and traverse servos) processing function, digital signal proce ssing function (efm demodulation and circ/ cd-rom error correction), digital servo processing function for spindle motor, anti-shock memory contro l function supporting 64-mbit, 16-mbit, 4-mbit, or 1-mbit dram that enables compression/decompression for a disc rotation synchronous playback (i.e. jitter free), a decode function for mp3, fs conversion processing function, a digital filter, and d/a converter . all the processing functions after the head amplifier (rf amplifier) are incorporated into a single chip. this lsi includes microsoft?s technology and cannot be used and distributed with out a license from microsoft corporation. ? features (optical servo) y focus, tracking, and traverse servos y automatic adjustment functions (focus / tracking gain, focus / track ing offset, focus / tracking balance) y provided with a countermeasure for dropout y provided with an anti - shock detection function y provided with a track - cross function y drive output pwm drive function supported y provided with supply voltage monitoring and a servo gain automatic adjustment function (digital signal processing) y containing dsl and analog / digital pll y provided with a frame synchronous de tection / protection / interpolation y subcode data processing q - data crc check on - chip q - data register on - chip cd-text data register y circ error correction c1 decoder : double error correction c2 decoder : triple / quadruple error correction on - chip deinterleaving 16 - k ram y cd-rom error correction q decoder : an error correction p decoder : an error correction mode1 and mode 2 compatible y audio data interpolation processing 4 - sampling average value interpolation and previous value hold (spindle motor servo) y clv digital servo y servo gain setting function y shaft loss compensation setting function (audio circuit) y soft muting y digital attenuation (2048 levels) y soft attenuation (2048 levels) y digital audio interface (eiaj format) y 8 - oversampling digital filter y on - chip low - voltage op amp
MN6627933 4 sdd00032aem (audio circuit) (continued) y bass boost filter, high - band notch filter, and surround function y on - chip digital de - emphasis (mp3 decoding) y decoding of signals recorded in mpeg1 - layer3 or mpeg2 - layer3 format y decoding of signals recorded in mpeg1 - layer2 or mpeg2 - layer2 format y decoding of signals recorded in mpeg2.5 format y sampling rate conversion from signals record ed at fs = 32 khz or 48 khz to 44.1 khz (sd interface) y stream serial input from sd available (anti-shock memory controller) y adpcm 4 - bit compression or expansion / deco mpression in full - bit ( 16 bits ) mode y external dram selectable async dram (data bus width : 4 bits) 64 - mbit dram 1 16 - mbit dram 2 16 - mbit dram 1 + 4 - mbit dram 1 16 - mbit dram 1 4 - mbit dram 2 4 - mbit dram 1 1 - mbit dram 2 1 - mbit dram 1 async dram (data bus width : 16 bits) 128 - mbit dram 1 64 - mbit dram 1 16 - mbit dram 1 4 - mbit dram 1 sdram (data bus width : 16 bits) 128 - mbit dram 1 64 - mbit dram 1 16 - mbit dram 1 4 - mbit dram 1 (others) y disc rotation mechanism has a synchronous playback (jitter - free) mode (? 50 % to + 50 %) y 8 - speed playback (when using jitter - free function) y tx output (1 -, 2 -, 3 - and 4 - speed) supported y serial data output pitch shift function a patent license must be acquired from the manage ment company when using mpeg layer3 products. ? applications y signal processing lsi for cds (compact discs)
MN6627933 5 sdd00032aem ? application circuit ? da converter
MN6627933 6 sdd00032aem ? block diagram ? da converter
MN6627933 7 sdd00032aem ? pin assignment 100 - pin flat package ( lqfp100 - p - 1414 )
MN6627933 8 sdd00032aem ? pin descriptions traverse drive signal output (positive polarity) o trvp 31 spindle drive signal output (polarity) o * sppol 30 spindle drive signal output (absolute value) o spout 29 power supply 1 for inte rnal digital circuits i dvdd1 28 sdram bank selection signal output 0 o * ba0 27 sdram bank selection signal output 1 o * ba1 26 dram address signal output 10 o a10 25 ground 1 for digital circuits i dvss1 24 power supply 1 for dram interface i/o i drvdd1 23 dram address signal output 0 o a0 22 dram address signal output 1 o a1 21 dram address signal output 2 o a2 20 dram address signal output 3 o a3 19 sdram chip select signal output o ncs 18 dram ras control signal output o nras 17 dram cas control signal output o ncas 16 dram write enable signal output o nwe 15 sdram lower byte data mask signal output o ldqm 14 dram address signal output 4 o a4 13 dram address signal output 5 o a5 12 dram address signal output 6 o a6 11 dram address signal output 7 o a7 10 dram address signal output 8 o a8 9 dram address signal output 9 o a9 8 dram address signal output 11 o a11 7 sdram clock signal output o sdrck 6 sdram upper byte data mask signal output o udqm 5 dram data signal i/o 8 i/o d8 4 dram data signal i/o 9 i/o d9 3 dram data signal i/o 10 i/o d10 2 dram data signal i/o 11 i/o d11 1 function i/o symbol pin no. note) pins marked with an asterisk can be switched to different signals by using microcontroller commands. the specifications o f the dram pins depend on their type and capacitance.
MN6627933 9 sdd00032aem function i/o symbol pin no. test monitor output 1 o tmon1 63 ? ? n. c. 62 power supply for line - out output i lovdd1 61 r - ch audio output for line - out output o looutr 60 ground for line - out output i lovss1 59 l - ch audio output for line - out output o looutl 58 traverse drive signal output (negative polarity) o * trvm 32 ground 1 for analog circuits i avss 57 pll loop filter pin (speed comparison output) o pllfo 56 pll loop filter pin (phase comparison output) o pllf 55 pwm output mode selection input low : direct high : 3 ? state i pwmsel 54 dsl loop filter pin o dslf 53 rf signal input i arf 52 analog reference current input i iref 51 power supply 1 for analog circuits i avdd 50 dropout signal input i bdo 49 off - track signal input i oft 48 rf detectoion signal input i nrfdet 47 laser on signal output o ldon 46 rf envelope signal input i rfenv 45 voltage input for s upply voltage monitor i adpvcc 44 tracking error signal input i te 43 focus error signal input i fe 42 focus balance adjustment signal output o fbal 41 tracking balance adjustment signal output o tbal 40 power supply 1 for digital i/o i iovdd1 39 focus drive signal output (negative polarity) o * fom 38 focus drive signal output (positive polarity) o fop 37 tracking drive signal output (negative polarity) o * trm 36 tracking drive signal output (positive polarity) o trp 35 traverse drive signal output 2 (negative polarity) o * trvm2 34 traverse drive signal output 2 (positive polarity) o * trvp2 33 note) pins marked with an asterisk can be switched to different signals by using microcontroller commands. ? pin descriptions (continued)
MN6627933 10 sdd00032aem dram data signal i/o 7 i/o d7 95 dram data signal i/o 6 i/o d6 94 dram data signal i/o 5 i/o d5 93 dram data signal i/o 4 i/o d4 92 dram data signal i/o 3 i/o d3 91 dram data signal i/o 0 i/o d0 90 dram data signal i/o 1 i/o d1 89 dram data signal i/o 2 i/o d2 88 power supply 2 for inte rnal digital circuits i dvdd2 87 power supply 2 for digital i/o i iovdd2 86 crystal oscillator circuit output o x2 85 crystal oscillator circuit input i x1 84 ground 3 for digital circuits i dvss3 83 test mode setting input i ntest 82 lsi reset signal input i nrst 81 ? ? n. c. 64 flag signal output o * flag 80 digital audio interface signal output o * tx 79 88.2 - khz clock signal output o * pmck 78 4.2336 - / 8.4672 - mhz clock signal output o * smck 77 subcode block clock signal output o * blkck 76 status signal output o * stat 75 microcontroller command load signal input i mld 74 microcontroller command data signal input i mdata 73 microcontroller command clock signal input i mclk 72 expansion i/o port 2 i/o * ext2 71 expansion i/o port 1 i/o * ext1 70 expansion i/o port 0 i/o * ext0 69 ground 2 for digital circuits i dvss2 68 power supply 3 for digital circuits i dvdd3 67 test monitor output 2 o tmon2 66 ? ? n. c. 65 function i/o symbol pin no. note) pins marked with an asterisk can be switched to different signals by using microcontroller commands. ? pin descriptions (continued)
MN6627933 11 sdd00032aem dram data signal i/o 15 i/o d15 96 dram data signal i/o 12 i/o d12 100 dram data signal i/o 13 i/o d13 99 power supply 2 for dram interface i/o i drvdd2 98 dram data signal i/o 14 i/o d14 97 function i/o symbol pin no. note) pins marked with an asteri sk can be switched to different signals by usi ng microcontroller commands. the specifications of the dram pins depend on their type and capacitance. note) if the mn6627932 and MN6627933 share the same pcb design, the followings are needed: pin 62 (n.c.): low fixed pin 64 (n.c.): lov dd2 applied pin 65 (n.c.): lov ss2 applied for details of the mn6627932, see the mn6627932 product standards and specifications documents. ? pin descriptions (continued)
MN6627933 12 sdd00032aem ? absolute maximum ratings dv ss1, 2, 3 = 0 v av ss = 0 v lov ss1 = 0 v mw 560 p d power dissipation a4 c ? 30 to + 85 t opr operating ambient temperature a5 c ? 50 to + 125 t stg storage temperature a6 note unit rating symbol parameter dv ss1, 2, 3 = 0 v av ss = 0 v lov ss1 = 0 v v dv ss1, 2, 3 ? 0.3 to drv dd1, 2 + 0.3 (upper limit : 4.6 v) dv ss1, 2, 3 ? 0.3 to io vdd1, 2 + 0.3 (upper limit : 4.6 v) av ss ? 0.3 to av dd + 0.3 (upper limit : 4.6 v) lov ss1 ? 0.3 to lov dd1 + 0.3 (upper limit : 4.6 v) v o output voltage a3 dv ss1, 2, 3 = 0 v av ss = 0 v lov ss1 = 0 v v dv ss1, 2, 3 ? 0.3 to drv dd1, 2 + 0.3 (upper limit : 4.6 v) dv ss1, 2, 3 ? 0.3 to iov dd1, 2 + 0.3 (upper limit : 4.6 v) av ss ? 0.3 to av dd + 0.3 (upper limit : 4.6 v) lov ss1 ? 0.3 to lov dd1 + 0.3 (upper limit : 4.6 v) v i input voltage a2 dv ss1, 2, 3 = 0 v av ss = 0 v lov ss1 = 0 v v ? 0.3 to + 4.6 drv dd1, 2 iov dd1, 2 av dd lov dd1 supply voltage a1 note) 1. the absolute maximum ratings are the li mit values beyond which the ic may be broken. they do not assure operations. 2. connect each of the dv ss1 , dv ss2 , dv ss3 , av ss , and lov ss1 pins directly to ground and use at the same voltage. 3. connect each of the drv dd1 , drv dd2 , iov dd1 , iov dd2 , av dd , and lov dd1 pins directly to the specified power supply and use at the same voltage. 4. drv dd1 , drv dd2 , iov dd1 , iov dd2 , av dd , and lov dd1 should be powered up at the same time. 5. this ic has a built-in regulator, and makes the power supply voltage of dv dd (digital system supply voltage) inside the ic. connect each of the dv dd1 , dv dd2 , and dv dd3 pins directly, and don't supply power to the dv dd1 , dv dd2 , and dv dd3 pins. 6. the built-in regulator is only for this ic's dv dd power. do not use for power supply for any ot her devices. also do not apply any external voltage to each of dv dd1 , dv dd2 , and dv dd3 pins. 7 connect a bypass capacitor of 10 f between each of iov dd2 and dv dd2 pins and dv ss , and connect a bypass capacitor of 0.1 f or larger between each of the power supply pins and ground. ? operating supply voltage range dv ss1, 2, 3 , av ss , lov ss1 = 0 v, t a = ? 30 c to + 85 c v 3.6 3.3 2.2 drv dd1, 2 d-ram interface voltage b4 v 3.6 3.3 2.4 lov dd1 audio system supply voltage b3 v 3.6 3.3 2.4 av dd analog system supply voltage b2 v 3.6 3.3 2.2 iov dd1, 2 i/o system supply voltage b1 max typ min unit limits conditions symbol parameter
MN6627933 13 sdd00032aem ? 100 rd b14 m ? 1 r1 recommended external feedback resistance b13 15 c2 recommended external capacitance 2 b12 pf 15 c1 recommended external capacitance 1 b11 mhz 33.8688 33.8688 mhz oscillator *3 fxtal oscillator frequency b10 self - excited oscillation 2 * 1 ? 470 rd b9 m ? 1 r1 recommended external feedback resistance b8 15 c2 recommended external capacitance 2 b7 pf 15 c1 recommended external capacitance 1 b6 mhz 16.9344 16.9344 mhz oscillator *2 fxtal oscillator frequency b5 self - excited oscillation 1 * 1 max typ min unit limits conditions symbol parameter note) *1: oscillation circuit *2: values for c1 and c2 specified above are standard values when use cstce16m9v53 made in murata manufacturing co., ltd. as an oscillator. however, cstce16m9v53 builds in c1 and c2 of the above standard value. the appropriate capacitors' values differ acc ording to the oscillator used. use the valu es specified by the oscillator manufact urer. *3: values for c1 and c2 specified above are standard values when use cstcg33m8v53 made in murata manufacturing co., ltd. as an oscillator. however, cstcg33m8v53 builds in c1 and c2 of the above standard value. the appropriate capacitors' values differ acc ording to the oscillator used. use the valu es specified by the oscillator manufact urer. cstce16m9v53, cstcg33m8v53 MN6627933cg c2 x2 o scillator c1 x1 r1 rd ? operating supply voltage range (continued) drv dd1, 2 , iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v
MN6627933 14 sdd00032aem ? electrical characteristics drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 1. dc characteristics mw 297 112.2 p t total power consumption c6 ma 90 34 anti - shock memory function used. no external load connected. (in 8 - speed playback mode) mp3 decode : off cd-rom decode : off digital pll : off i dd supply current c5 mw 231 92.4 p t total power consumption c4 ma 68 22 anti - shock memory function used. no external load connected. (in 2 - speed playback mode) adpcm compression : on mp3 decode : off cd-rom decode : off digital pll : off i dd supply current c1 mw 224.4 82.5 p t total power consumption c2 ma 70 28 anti - shock memory function used. no external load connected. (in 4 - speed playback mode) mp3 decode : on cd-rom decode : on digital pll : off i dd supply current c3 limits typ unit max conditions min symbol parameter
MN6627933 15 sdd00032aem a 10 v in = 0 v or 3.3 v i lk4 input leakage current c18 v 0.99 0.0 v il4 low - level input voltage c17 v 3.30 2.31 v ih4 high - level input voltage c16 input pins ntest a 1 v in = 0 v or 3.3 v i lk3 input leakage current c15 v 0.99 0.0 v il3 low - level input voltage c14 v 3.30 2.31 v ih3 high - level input voltage c13 input pins 3 av dd voltage type nrfdet, oft , bdo, pwmsel a 1 v in = 0 v or 3.3 v i lk2 input leakage current c12 v 0.99 0.0 v il2 low - level input voltage c11 v 3.30 2.31 v ih2 high - level input voltage c10 input pins 2 iov dd voltage type ext0, ext1, ext2, mclk, mdata, mld, nrst a 1 v in = 0 v or 3.3 v i lk1 input leakage current c9 v 0.99 0.0 v il1 low - level input voltage c8 v 3.30 2.31 v ih1 high - level input voltage c7 input pins 1 drv dd voltage type d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15 limits typ unit max conditions min symbol parameter ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 1. dc characteristics (continued)
MN6627933 16 sdd00032aem v v v v v a 1 hi-z state v o = 0 v or 3.3 v o lk5 output leakage current c31 0.4 i ol5 = 1.0 ma v ol5 low - level output voltage c30 v 2.7 i oh5 = ? 1.0 ma v oh5 high - level output voltage c29 output pins 5 av dd voltage type ldon a 1 hi-z state v o = 0 v or 3.3 v o lk4 output leakage current c28 0.4 i ol4 = 1.0 ma v ol4 low - level output voltage c27 v 2.7 i oh4 = ? 1.0 ma v oh4 high - level output voltage c26 output pin 4 iov dd voltage type spout, trvp, trvp2 , trvm2, trp, fop, tmon1, tmon2, ext0, ext1, ext2, blkck, smck, pmck, flag 0.4 i ol3 = 1.0 ma v ol3 low - level output voltage c25 v 2.7 i oh3 = ? 1.0 ma v oh3 high - level output voltage c24 output pins 3 iov dd voltage type sppol, trvm, trm, fom, stat, tx a 1 hi-z state v o = 0 v or 3.3 v o lk2 output leakage current c23 0.4 i ol2 = 1.0 ma v ol2 low - level output voltage c22 v 2.7 i oh2 = ? 1.0 ma v oh2 high - level output voltage c21 output pins 2 drv dd voltage type ba0, ba1 0.4 i ol1 = 1.0 ma v ol1 low - level output voltage c20 v 2.7 i oh1 = ? 1.0 ma v oh1 high - level output voltage c19 output pins 1 drv dd voltage type d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, udqm, ldqm, sdrck, nwe, ncas, nras, ncs limits typ unit max conditions min symbol parameter ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 1. dc characteristics (continued)
MN6627933 17 sdd00032aem lsb v k ? 135 100 65 regsel: r1 + r2 + r3 setting 54 40 26 regsel: r2 + r3 setting 27 20 13 regsel: r3 setting 3 dnl differential nonlinearity c39 lsb 2 a/d output = 99 to 66 ( 2's complement ) inl integral nonlinearity c38 bit 8 res resolution c37 a/d converter (for servo) 0.33 v il4 low - level input voltage c36 v 2.97 v ih4 high - level input voltage c35 analog system input pin 3 te, fe, rfenv, adpv cc 68 50 32 regsel: r1 + r2 + r3 and rfsw = on setting r arf internal resistance between arf and dslf pins c34 v [p-p] 1.0 0.5 efm signal input level in an application circuit of dsl block. v arf nput signal amplitude c33 analog system input pin 2 arf a 41 29 18 when pulled up with an 82 - k ? resistor. i ref input current c32 analog system input pin 1 i ref limits typ unit max conditions min symbol parameter ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 1. dc characteristics (continued)
MN6627933 18 sdd00032aem a a a a a a a ?15 ?22 ?29 at default setting ( 1 ) i bal output current ( p ) c52 a 104 80 56 pllf = 1.65 v i pfh phase comparator output current ( n ) c43 ?56 ?80 ? 104 pllf = 1.65 v i pfh phase comparator output current ( p ) c44 1 hi-z state i lkp input leakage current c45 10 0 ?10 pllf = 1.65 v i plbl output unbalance current c46 a 104 80 56 bdo: low, tracking on state dslf = 1.65 v i dsh output current ( n ) c40 ?56 ?80 ? 104 bdo: low, tracking on state dslf = 1.65 v i dsh output current ( p ) c41 a 29 22 15 at default setting ( 1 ) i bah output current ( n ) c51 analog system output pin 4: tbal, fbal ( i ref pin is pulled up to av dd with an 82 - k ? resistor ) 1 hi-z state i lkpo input leakage current c50 ?59 ?85 ? 111 i pfho output current ( p ) c49 a 111 85 59 i pfho output current ( n ) c48 analog system output pin 3: pllfo ( i ref pin is pulled up to av dd with an 82 - k ? resistor ) mhz 103.7 25.9 f vco 1 vco oscillator frequency for pll c47 analog system output pin 2: pllf ( i ref pin is pulled up to av dd with an 82 - k ? resistor ) 7 0 ?7 bdo: low, tracking on state normal current mode i dsel output unbalance current c42 analog system output pin 1: dslf ( i ref pin is pulled up to av dd with an 82 - k ? resistor ) limits typ unit max conditions min symbol parameter ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 1. dc characteristics (continued)
MN6627933 19 sdd00032aem drv dd1, 2 = 3.3 v, iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v av dd = 3.3 v, av ss = 0 v lov dd1 = 3.3 v, lov ss1 = 0 v recommended circuit fo r dsl and pll blocks note) the above is a basic circuit. calcul ate the constants and other factors of the circuit in consideration of playability whe n making use of this circuit for actual applications. iref 3.3 v arf dslf pllf pllfo 82 k ? 0.1 f 0.022 f 680 pf v arf 1.0 v[p-p] (typ.) 1000 pf 0.082 f 820 ?
MN6627933 20 sdd00032aem v[rms] 1.07 0.88 0.69 1 khz f.s. *4 output level 2 c59 db + 0.99 ?0.99 difference between outl and outr pins at output level 20 log ( v r / v l ) output level difference c58 v[rms] 1.62 1.33 1.04 1 khz f. s. *3 output level 1 c57 db 85 80 eiaj crosstalk c56 % 0.009 0.005 eiaj thd + n total harmonic distortion ratio c55 db 94 86 eiaj d. r. dynamic range c54 db 97 90 eiaj s/n signal - to - noise ratio c53 d/a converter analog characteristics * 1, 2 max typ min unit limits conditions symbol parameter note) *1: the analog characteristics show th e measured values when inserting a 15 ? resistor between lov dd1 and power supply. the above typical values are only reference values and not guaranteed. *2: with no anti-shock memory function used, th e operation of the d/a converter will not be guaranteed in modes other than norma l-speed playback. *3: the output level 1 shows the measured value at the output pin of the application circuit below. *4: the output level 2 shows a value at the output pin of the ic an d is calculated by taking the measured value of output level 1 , dividing it by the circuit gain. ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 1. dc characteristics (continued)
MN6627933 21 sdd00032aem mv[p-p] 30 v nz ripple noise amplitude c62 mv[p-p] 15 v rip ripple amplitude c61 power supply ripple noise * 2 s 200 t nrstl nrst pulse width c60 reset timing * 1 limits typ unit max conditions min symbol parameter note) *1: when the power is turned on, reset with the nrst pul se which is equal to or exceeds the above pulse width only after th e clock oscillation is stabilized within 10% of error of the specified oscillator frequency . keep noise on the reset line as low as possible. note) *2: the standard ripple noise values of the ic are guarante ed on condition that the values apply to typical 50-hz to 100-hz ripples with 500-khz typical noise and that both the ripples and noi se are in sine waveform as shown below. the values, however, vary under the influence of other parts located on the pcb. therefore, be sure to apply the ic to practical ap plications and check the actual ripple noise values. v nz v rip n oise frequency: 500 khz ripple frequency: 50 hz to 100 hz ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics nrst t nrstl 0.2v dd 0.2v dd
MN6627933 22 sdd00032aem ns 250 t r1 rise time c63 ns 50 t f2 fall time c66 ns 50 t r2 rise time c65 transition time 2 sbck, txtck * ns 250 t f1 fall time c64 transition time 1 mclk, mld limits typ unit max conditions min symbol parameter note) *: sbck and txtck are input from ext1. 0.7iov dd 0.3iov dd 0.7iov dd 0.3iov dd t r1,2 f1,2 t ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued)
MN6627933 23 sdd00032aem ns 300 t ckd mclk delay time c73 s 10 0.5 t ldw latch pulse time c72 ns 300 t ldd mld delay time c71 mhz 2 f mclk clock frequency c67 ns 150 t dh data hold time c70 ns 150 t dsu data setup time c69 ns 150 t ch,cl clock pulse width c68 microcontroller command input timing limits typ unit max conditions min symbol parameter mclk mdata mld 1 / f mclk t ch t cl t dsu t dh t ldw t ckd t ldd ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued)
MN6627933 24 sdd00032aem ns 150 t sd setup delay time c78 ns 173 when no filter is used. *2 ns 909 t ck clock width c74 ns 350 when digital filter is used. *2 t sbd delay time c77 ns 400 t ckl low-level pulse width c76 ns 400 t ckh high-level pulse width c75 subcode interface sbck, subc, txncldck * 1 limits typ unit max conditions min symbol parameter note) *1: sbck is output from ext1, subc is output from ext0, and txncldck is output from ext2. *2: sbck,txtck noise filter command is sbcknf ( by setting the d5 and d4 bits of the 67 command ) . ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued) txncldck sbck subc ncldck t ck t ckl t ckh t sd t sbd
MN6627933 25 sdd00032aem ns 1100 t sd setup delay time c83 ns 1150 t sbd delay time c82 ns 2500 t ck clock frequency c79 ns 1200 t ckl low-level pulse width c81 ns 1200 t ckh high-level pulse width c80 subcode interface txtck, txtd, dqsy * limits typ unit max conditions min symbol parameter note) 1. *: txtck is input or output from ext1, txtd is output from ext0, and txncldck is output from ext2. 2. the cycle width of the readout clock txtck is proportional to disc rotation speed. high-speed readout such as high-speed clv playback or high-speed jitter-free playback us ing mson (memory system setting) is pos sible. example) when in 2x speed mode t sbd2 = 450 ns (typ.) t ck t ckl t ckh t sd t sbd dqsy txtd txtck ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued)
MN6627933 26 sdd00032aem ns 173 t mtd delay time c95 ns 220 t mtl low-level pulse width c94 ns 220 t mth high-level pulse width c93 ns 500 t mt clock width c92 stat output interface ( when no noise filter is used. ) * 1, 2 ns 200 t mtd delay time c91 ns 220 t mtl low-level pulse width c90 ns 220 t mth high-level pulse width c89 ns 500 t mt clock width c88 stat output interface ( w hen analog filter 2 is used. ) * 1, 2 ns 225 t mtd delay time c87 ns 909 t mt clock width c84 ns 300 t mtl low-level pulse width c86 ns 300 t mth high-level pulse width c85 stat output interface ( w hen analog filter 1 is used. ) * 1, 2 limits typ unit max conditions min symbol parameter note) *1: in multiple-byte read mode using regrd command ( 96h ), vwa_id command ( 97h ), or vwai drd command ( 98h ), it is necess ary to set the high-level pulse width t mth to more than 450 ns in 1-byte increments. *2: mclk,mdata,mld noise filter command is mcifnf ( by setting the d5 and d4 bits of the 67 command ) . ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued) t mtd t mt t mtl t mth mclk stat
MN6627933 27 sdd00032aem ns 15 t hd hold time c110 ns 15 t st setup time c109 ns 29.5 t bclkl low-level pulse width c108 ns 29.5 t bclkh high-level pulse width c107 ns 59 in 8x-speed playback mode ( 48fs ) t bclk clock width c106 d/a output interface 3 ns 30 t hd hold time c105 ns 30 t st setup time c104 ns 59 t bclkl low-level pulse width c103 ns 59 t bclkh high-level pulse width c102 ns 118 in 4x-speed playback mode ( 48fs ) t bclk clock width c101 d/a output interface 2 ns 70 t hd hold time c100 ns 70 t st setup time c99 ns 354 in normal-speed playback mode ( 64fs ) t bclk clock width c96 ns 177 t bclkl low-level pulse width c98 ns 177 t bclkh high-level pulse width c97 d/a output interface 1 limits typ unit max conditions min symbol parameter note) srdata, bclk, and lrck are output in combination with pm ck (bclk), flag (srdata), and smck (lrck) or ext0 (srdata), ext1 (lrck), and ext2 (bclk). ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued) d/a output interface bclk srdata lrck t st t hd t bclkl t bclkh t bclk
MN6627933 28 sdd00032aem khz 44.1 f lrck lrck frequency c115 ns 100 t dh data hold time c114 ns 100 t dsu data setup time c113 ns 100 t ch,cl sclk pulse width c112 ns 2.8 f bclk bclk frequency c111 ns 150 t ch,cl sclk pulse width c118 ns 2.8 f bclk bclk frequency c117 d/a converter input timing 2 ( w hen digital filter is used. ) * 1, 2 ns 100 t bl, t lb bclk-lrck timing c116 ns 100 t bl, t lb bclk-lrck timing c122 khz 44.1 f lrck lrck frequency c121 ns 100 t dh data hold time c120 ns 100 t dsu data setup time c119 d/a converter input timing 1 ( w hen no noise filter is used. ) * 1, 2 limits typ unit max conditions min symbol parameter note) *1: srdatain, bclk, lrck noise filter command is srdat anf ( by setting the d7 and d6 bits of the 67 command ) . *2: srdatain, lrckin, and bclkin are input from ext0 ( srdatain ), ext1 ( lrckin ), and ext2 ( bclkin ) respectively. ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued) bclkin srdatain lrckin 1/f bclk ch cl bl lb lrck bl lb t dsu dh t t t tt 1/f t t
MN6627933 29 sdd00032aem cycle 5 t rcas refresh cas low-level pulse width c139 cycle 4 t rras refresh ras low-level pulse width c138 cycle 1 t crd cas-ras delay time c137 edo, first-page dram interface cas before ras refresh cycle 2 t rsh ras hold time c136 cycle 2 t cas cas low-level pulse width c135 cycle 1 t cp cas pre-charge pulse width c134 edo, first-page dram interface page mode data transfer cycle 2 t dwdh d0 to d15 write data hold time c133 cycle 1 t dwds d0 to d15 write data setup time c132 cycle 2 t wch write enable signal nwe hold time c131 cycle 2 t wcs write enable signal nwe setup time c130 cycle 2 t cac cas access time c129 cycle 4 t rac ras access time c128 cycle 2 t rcd ras - cas delay time ( ncas0, ncas1 ) c127 cycle 2 t cah a0 to a11 column address hold time c126 cycle 1 t asc a0 to a11 column address setup time c125 cycle 1 t rah a0 to a11 row address hold time c124 cycle 2 t asr a0 to a11 row address setup time c123 edo, first-page dram interface read / write cycle limits typ unit max conditions min symbol parameter note) one cycle is the system clock cycle of 1 / (16.9344 mhz or 33.8688 mhz) [s]. the system clock frequencies, 16.9344 mhz and 33.8688 mhz, are determined according to the dcksel command (65h command d6 and d 5). ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 1. ac characteristics (continued) (in bcksel = 0 mode)
MN6627933 30 sdd00032aem cycle 5 t rcas refresh cas low-level pulse width c156 cycle 4 t rras refresh ras low-level pulse width c155 cycle 1 t crd cas - ras delay time c154 edo, first-page dram interface cas before ras refresh cycle 1 t rsh ras hold time c153 cycle 1 t cas cas low-level pulse width c152 cycle 1 t cp cas pre-charge pulse width c151 edo, first-page dram interface page mode data transfer cycle 1 t dwdh d0 to d15 write data hold time c150 cycle 1 t dwds d0 to d15 write data setup time c149 cycle 1 t wch write enable signal nwe hold time c148 cycle 2 t wcs write enable signal nwe setup time c147 cycle 1 t cac cas access time c146 cycle 4 t rac ras access time c145 cycle 2 t rcd ras - cas delay time (ncas0, ncas1) c144 cycle 1 t cah a0 to a11 column address hold time c143 cycle 1 t asc a0 to a11 column address setup time c142 cycle 1 t rah a0 to a11 row address hold time c141 cycle 2 t asr a0 to a11 row address setup time c140 edo, first-page dram interface read / write cycle limits typ unit max conditions min symbol parameter note) one cycle is the system clock cycle of 1 / (16.9344 mhz or 33.8688 mhz) [s]. the system clock frequencies, 16.9344 mhz and 33.8688 mhz, are determined according to the dcksel command (65h command d6 and d 5). ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued) (in bcksel = 1 mode)
MN6627933 31 sdd00032aem edo, first-page dram access timing ( nras, ncas0, ncas1, nwe, a0 to a11, d0 to d15 ) < normal mode > t dwds t cac t asr row address column address a11 to a0 nras ncas0, ncas1 nwe(= h) d15 to d0 nwe d15 to d0 t rah t asc t cah t rcd t rac t wcs t wch t dwdh read write
MN6627933 32 sdd00032aem < page mode > < cas before ras refresh mode > t cp t cas t dwds t dwdh column address row address a11 to a0 nras ncas0, ncas1 nwe(= h) d15 to d0 column address column address nwe d15 to d0 t rsh t asc t cah t cac read write nras ncas0, ncas1 t crd t rras t rcas
MN6627933 33 sdd00032aem cycle 1 t ah a0 to a11, ba0, ba1 input hold time c173 cycle 1 t as a0 to a11, ba0, ba1 input setup time c172 cycle 1 t dqh d0 to d15 input hold time c171 cycle 1 t dqs d0 to d15 input setup time c170 cycle 0.5 t dmh ldqm, udqm input hold time c169 cycle 0.5 t dms ldqm, udqm input setup time c168 cycle 0.5 t weh new input hold time c167 cycle 0.5 t wes new input setup time c166 cycle 0.5 t cah ncas input hold time c165 cycle 0.5 t cas ncas input setup time c164 cycle 0.5 t rah nras input hold time c163 cycle 0.5 t ras nras input setup time c162 cycle 0.5 t csh ncs input hold time c161 cycle 0.5 t css ncs input setup time c160 cycle 0.5 t cl sdrck low-level pulse width c159 cycle 0.5 t ch sdrck high-level pulse width c158 cycle 1 t clk sdrck cycle time c157 sdram interface limits typ unit max conditions min symbol parameter note) 1. one cycle is the system clock cycle of 1 / (16.9344 mhz or 33.8688 mhz) [s]. 2. connect sdram near this lsi as much as possible. connect the wiring load of the sdrck pin specially within 5 pf. ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued)
MN6627933 34 sdd00032aem ns 0 t ohz high impedance output time from sdrck c177 ns 0 t olz low impedance output time from sdrck c176 ns 0 t oh hi-z output time from sdrck c175 ns 15 t ac access time from sdrck c174 sdram interface limits typ unit max conditions min symbol parameter note) one cycle is the system clock cycle of 1 / (16.9344 mhz or 33.8688 mhz) [s]. ? electrical characteristics (continued) drv dd1, 2 ,iov dd1, 2 = 3.3 v, dv ss1, 2, 3 = 0 v, av dd = 3.3 v, av ss = 0 v, lov dd1 = 3.3 v, lov ss1 = 0 v 2. ac characteristics (continued)
MN6627933 35 sdd00032aem sdram access timing ( sdrck, ncs, ncas, nwe, ld qm, udqm, a0 to a11, ba0, ba1, d0 to d15 ) write sdrck d0 to d15 ncs nras ncas t clk t ch t cl t css t csh t ras t rah t cas t cah nwe t wes t weh udqm ldqm t dms t dms t dmh t dmh valid t dqs t dqh a0 to a11, ba0, ba1 rasaddress casaddress t as t ah t as t ah
MN6627933 36 sdd00032aem read sdrck d0 to d15 ncs nras ncas t clk t ch t cl t css t csh t ras t rah t cas t cah t wes t weh udqm ldqm t dms t dms t dmh t dmh output decision t olz t ac a0 to a11, ba0, ba1 rasaddress casaddress t as t ah t as t ah : invalid data t ohz t oh
MN6627933 37 sdd00032aem sdram initialize sequence ( sdrck, ncs, ncas, nwe, a0 to a11, ba0, ba1 ) ncas 10 to 15 cycle pall ref ref ref mrs 6cycle 6cycle 16 refresh nrst sdrck ncs nras nwr ba0, ba1 a0 to a11 ???.
MN6627933 38 sdd00032aem sdram page access timing ( sdrck, ncs, nras, ncas, nwe, a0 to a11, ba0, ba1 ) write sdrck d0 to d15 ncs nras ncas udqm ldqm a0 to a11, ba0, ba1 nwe valid1 valid2 rasaddress casaddress1 casaddress2 nwe valid1 valid2 d0 to d15 row address column address column address ...... precharge read
request for your special attention and precautions in using the technical information and semiconductors described in this material (1) an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technical information described in this material and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. (2) the technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. it neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) we are not liable for the infringement of rights owned by a third party arising out of the use of the technical information as described in this material. (4) the products described in this material are intended to be used for standard applications or general elec- tronic equipment (such as office equipment, communications equipment, measuring instruments and house- hold appliances). consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combus- tion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. ? any applications other than the standard applications intended. (5) the products and product specifications described in this material are subject to change without notice for modification and/or improvement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifica- tions satisfy your requirements. (6) when designing your equipment, comply with the guaranteed values, in particular those of maximum rat- ing, the range of operating power supply voltage, and heat radiation characteristics. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) when using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) this material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of matsushita electric industrial co., ltd. 2003 sep

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